Prior programmable memories have been implemented using split-gate non-volatile memory (NVM) cells. While it is desirable to shrink device geometries for such split-gate NVM cells, high resistance between control gates and underlying channels for split-gate NVM cells can become problematic for NVM system performance.
FIG. 1 (Prior Art) is a cross-section view of an embodiment 100 for a prior split-gate NVM cell. A select gate (SG) 104, a charge storage layer 108, and a control gate (CG) 106 have been formed over a substrate 102 along with select-gate dielectric layer 114 and protective nitride layer 105. Source (S) region 110 and drain (D) region 112, as well as spacers 120, 122, and 124, have also been formed. During operation, particularly as device geometries are reduced, high resistance (e.g., reduced transconductance) can occur between the corner of the control gate 106 and the underlying channel next to the select gate 104 as indicated by arrow 120. This reduced transconductance can cause undesirable performance degradation of the NVM system.
FIG. 11 (Prior Art) is a cross-section view of an embodiment 1100 for a prior split-gate NVM cell where the control gate (CG) 106 is formed prior to forming the select gate (SG) 104. A control gate (CG) 106, a charge storage layer 108, and a select gate (SG) 104 have been formed over a substrate 102 along with a select-gate dielectric layer 114 and protective nitride layer 105. Source (S) region 110 and drain (D) region 112, as well as spacers 120, 122, and 124, have also been formed. During operation, particularly as device geometries are reduced, high resistance (e.g., reduced transconductance) can occur between the corner of the select gate 104 and the underlying channel next to the control gate 106 as indicated by arrow 120. This reduced transconductance can cause undesirable performance degradation of the NVM system.